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HC5517B
Data Sheet July 1998 File Number
4404.2
Low Cost 3 REN Ringing SLIC for ISDN Modem/TA and WL
The HC5517B low cost, 3 REN ringing SLIC is designed to accommodate a wide variety of short loop applications and provides the same degree of flexibility as the high performance HC5517. The flexible features include open circuit tip to ring DC voltages, user defined ringing waveforms, ring trip detection thresholds, and loop current limits that can be tailored for many applications. Additional features of the HC5517B are complex impedance matching, pulse metering, and transhybrid balance. The HC5517B is designed for use in short loop, low cost systems where traditional ring generation is not economically feasible. The device is manufactured in a high voltage Dielectric Isolation (DI) process. The DI process provides substrate latch up immunity, resulting in a robust system design. A thermal shutdown with an alarm output and line fault protection are also included for operation in harsh environments.
Features
* Load Drive Capability . . . . . . . . . . . . . . . . . . . . . . . 3 REN * Trapezoidal, Square or Sine Wave Capability * Ringing from -80V Battery . . . . . . . . . . . . . . . . . . . 75VP-P * Ringing from -75V Battery . . . . . . . . . . . . . . . . . . . 70VP-P * Ringing Current Independent of Loop Current Setting * Ringing Crest Factor Independent of REN Loading * Latchup Immune to Inductive Kick Back and Hot Plug * Fax, Answering Machine and MTU Compatible * Resistive and Complex Impedance Matching * Programmable Loop Current Limit * Switch Hook, Ring Trip and Ground Key Detection * Single Low Voltage +5V Supply
Applications
* Solid State Line Interface Circuit for Hybrid Fiber Coax, Set Top Box, Voice/Data Modems
Ordering Information
PART NUMBER HC5517BCM HC5517BCB TEMP. RANGE (oC) 0 to 75 0 to 75 PACKAGE 28 Ld PLCC 28 SOIC PKG. NO. N28.45 M28.3
* Related Literature - AN9607, Impedance Matching Design Equations - AN9628, AC Voltage Gain - AN9636, Implementing an Analog Port for ISDN - AN549, The HC-5502/4X Telephone SLIC
Block Diagram
VRX VTX VRING + FAULT DETECTOR CURRENT LIMIT RING TRIP DETECTOR BIAS AGND BGND F1 F0 RS TST IIL LOGIC INTERFACE RELAY DRIVER RDI SHD ALM ILIMIT RTD RDO
TIP FEED TIP SENSE 2-WIRE INTERFACE
4-WIRE INTERFACE
RING FEED RING SENSE 1 RING SENSE 2 VREF RTI VBAT VCC
LOOP CURRENT DETECTOR
-
- IN 1
OUT 1
61
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
HC5517B
Absolute Maximum Ratings
TA = 25oC
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) PLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Maximum Junction Temperature, Plastic Packages. . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (SOIC, PLCC - Lead Tips Only)
Maximum Supply Voltages (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V (VCC)-(VBAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90V Relay Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +15V
Operating Conditions
Temperature Range HC5517BCM, HC5517BCB . . . . . . . . . . . . . . . . . . . . 0oC to 75oC Relay Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V to +12V Positive Power Supply (VCC) . . . . . . . . . . . . . . . . . . . . . . . +5V 5% Negative Power Supply (VBAT) . . . . . . . . . . . . . . . . . . .-16V to -80V
Die Characteristics
Transistor Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 Diode Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Die Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 x 120 Substrate Potential. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VBAT Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bipolar-DI ESD (Human Body Model) . . . . . . . . . . . . . . . . . . . . . . . . . . . .500V
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied
NOTES: 1. JA is measured with the component mounted on an evaluation board PC board in free air. 2. All grounds (AGND, BGND) must be applied before VCC or VBAT . Failure to do so may result in premature failure of the part. If a user wishes to run separate grounds off a line card, the AGND must be applied first.
Electrical Specifications
Unless Otherwise Specified, Typical Parameters are at TA = 25oC, Min-Max Parameters are over Operating Temperature Range, VBAT = -24V, VCC = +5V, AGND = BGND = 0V. All AC Parameters are specified at 600 2-Wire Terminating Impedance TEST CONDITIONS MIN TYP MAX UNITS
PARAMETER RINGING TRANSMISSION PARAMETERS VRING Input Impedance 4-Wire to 2-Wire Gain AC TRANSMISSION PARAMETERS RX Input Impedance TX Output Impedance 4-Wire Input Overload Level 2-Wire Return Loss SRL LO ERL SRL HI 2-Wire Longitudinal to Metallic Balance Off Hook 4-Wire Longitudinal Balance Off Hook Low Frequency Longitudinal Balance Longitudinal Current Capability Insertion Loss 2-Wire/4-Wire (Includes External Transhybrid Amplifier with a Gain of 2.4) 4-Wire/2-Wire 4-Wire/4-Wire (Includes External Transhybrid Amplifier with a Gain of 2.4) (Note 3)
5.4 40
k V/V
VRING to Vt-r (Note 3)
300Hz to 3.4kHz (Note 3) 300Hz to 3.4kHz (Note 3) 300Hz to 3.4kHz RL = 1200, 600 Reference (Note 3) Matched for 600 (Note 3) 26 30 30 Per ANSI/IEEE STD 455-1976 (Note 3) 300Hz to 3400Hz 300Hz to 3400Hz (Note 3) ILINE = 40mA TA = 25oC (Note 3) ILINE = 40mA TA = 25oC (Note 3) 0dBm at 1kHz, Referenced 600 40 40 +1.0
108 20
k VPEAK
35 40 40
dB dB dB dB dB
10
23 40
dBrnc mARMS
0.05 0.05
0.2 0.2 0.35
dB dB dB
62
HC5517B
Electrical Specifications
Unless Otherwise Specified, Typical Parameters are at TA = 25oC, Min-Max Parameters are over Operating Temperature Range, VBAT = -24V, VCC = +5V, AGND = BGND = 0V. All AC Parameters are specified at 600 2-Wire Terminating Impedance (Continued) TEST CONDITIONS 300Hz to 3400Hz (Note 3) Referenced to Absolute Level at 1kHz, 0dBm Referenced 600 Referenced to -10dBm (Note 3) +3 to -40dBm -40 to -50dBm -50 to -55dBm Absolute Delay 2-Wire/4-Wire 4-Wire/2-Wire 4-Wire/4-Wire Transhybrid Loss Total Harmonic Distortion 2-Wire/4-Wire, 4-Wire/2-Wire, 4-Wire/4-Wire Idle Channel Noise 2-Wire and 4-Wire (Note 3) 300Hz to 3400Hz 300Hz to 3400Hz 300Hz to 3400Hz VIN = 1VP-P at 1kHz (Note 3,4) Reference Level 0dBm at 600 300Hz to 3400Hz (Note 3) (Note 3) C-Message Psophometric (Note 3) Power Supply Rejection Ratio VCC to 2-Wire VCC to 4-Wire VBAT to 2-Wire VBAT to 4-Wire VCC to 2-Wire VCC to 4-Wire VBAT to 2-Wire VBAT to 4-Wire DC PARAMETERS Loop Current Programming Limit Range Accuracy Loop Current During Power Denial Fault Currents TIP to Ground (Note 3) RING to Ground TIP and RING to Ground (Note 3) Switch Hook Detection Threshold Ring Trip Comparator Voltage Threshold Thermal ALARM Output (Note 3) Dial Pulse Distortion (Note 3) Safe Operating Die Temperature Exceeded -0.28 140 30 120 150 12 -0.24 0.1 15 -0.22 160 0.5 mA mA mA mA V
oC
PARAMETER Frequency Response Level Linearity 2-Wire to 4-Wire and 4-Wire to 2-Wire
MIN -
TYP 0.02
MAX 0.06
UNITS dB
-
-
0.08 0.12 0.3
dB dB dB s s s dB dB dBrnC dBmp
30 -
0.95 40 3 -87
1.0 1.0 1.5 -50 -
(Note 3) 30Hz to 200Hz, RL = 600
20 20 20 20
40 40 40 50 40 28 50 50
-
dB dB dB dB dB dB dB dB
(Note 3) 200Hz to 16kHz, RL = 600
30 20 20 20
20 (Note 5) 15 RL = 200 -
4
60 7
mA % mA
ms
63
HC5517B
Electrical Specifications
Unless Otherwise Specified, Typical Parameters are at TA = 25oC, Min-Max Parameters are over Operating Temperature Range, VBAT = -24V, VCC = +5V, AGND = BGND = 0V. All AC Parameters are specified at 600 2-Wire Terminating Impedance (Continued) TEST CONDITIONS MIN TYP MAX UNITS
PARAMETER Uncommitted Relay Driver On Voltage VOL Off Leakage Current TTL/CMOS Logic Inputs (F0, F1, RS, TST, RDI) Logic `0' VIL Logic `1' VIH Input Current (F0, F1, RS, TST, RDI) Input Current (F0, F1, RS, TST, RDI) Logic Outputs Logic `0' VOL Logic `1' VOH Power Dissipation On Hook
IOL (RDO) = 30mA
-
0.2 10
0.5 100
V A
0 2.0 IIH, 0V VIN 5V IIL, 0V VIN 5V -
-
0.8 5.5 -1 -100
V V A A
ILOAD = 800A ILOAD = 40A VCC = +5V, VBAT = -80V, RLOOP = VCC = +5V, VBAT = -48V, RLOOP =
2.7
0.3 300 150 280 3 2 1.9 3.6 2.6 1.8
0.6 6 5 4 7 6 4
V V mW mW mW mA mA mA mA mA mA

-
Power Dissipation Off Hook ICC
VCC = +5V, VBAT = -24V, RLOOP = 600, IL = 25mA VCC = +5V, VBAT = -80V, RLOOP = VCC = +5V, VBAT = -48V, RLOOP = VCC = +5V, VBAT = -24V, RLOOP =

IBAT
VCC = +5V, VB- = -80V, RLOOP = VCC = +5V, VB- = -48V, RLOOP = VCC = +5V, VB- = -24V, RLOOP =

UNCOMMITTED OP AMP PARAMETERS Input Offset Voltage Input Offset Current Differential Input Resistance (Note 3) Output Voltage Swing (Note 3) Small Signal GBW (Note 3) NOTES: 3. These parameters are controlled by design or process parameters and are not directly tested. These parameters are characterized upon initial design release, upon design changes which would affect these characteristics, and at intervals to assure product quality and specification compliance. 4. For transhybrid circuit as shown in Figure 3. 5. Application limitation based on maximum switch hook detect limit and metallic currents. Not a part limitation. RL = 10k 5 10 1 3 1 mV nA M VP-P MHz
64
HC5517B
R TF R
VRX 17
OUT 1 12
-IN 1 13
VRING 24
VTX 19
VCC 2
AGND 1 BIAS NETWORK 22
TF
25
+
R R/2 +2V R/20 R R 2R
BGND
+
OP AMP
27 4 5
VBAT
F1 F0 RS TST
4.5K 100K RING SENSE 1 RING SENSE 2 15 100K 100K 16 100K 4.5K 90K + 25K FAULT DET 25K RA RTD
THERM LTD
TSD
IIL LOGIC INTERFACE
TIP SENSE
14
R R
+ 2R
-
TA SHD SH
6 9
GK
-
7 8 RFC 10
SHD RTD ALM RDO
90K 26 RF
RF
+
-
90K
GM VB/2 REF 18 NU 28 RTI
+
-
RF2
21
R = 108k
3 VREF
11 ILIMIT
20 RDI
HC5517B DEVICE TRUTH TABLE F1 0 0 F0 0 1 STATE Loop power Denial Active Power Down Latch RESET, Power on RESET RD Active (unbalanced ringing) Normal Loop feed
Power Dissipation Careful thermal design is required to guarantee that the maximum junction temperature of 150oC of the device is not exceeded. The junction temperature of the SLIC can be calculated using:
T J = T A + JA ( I CC V CC + I BAT V BAT - ( ( I LOOP ) * R LOOP ) ) (EQ. 1)
2
1 1
0 1
The truth table for the internal logic of the HC5517B is provided in the above table. This family of ringing SLICs can be configured to support traditional unbalanced ringing and through SLIC balanced ringing. The device operating states used by through SLIC ringing applications are loop power denial and normal feed. During loop power denial, the tip and ring amplifiers are disabled (high impedance) and the DC voltage of each amplifier approaches ground. The SLIC will not provide current to the subscriber loop during this mode and will not detect loop closure. Voice transmission occurs during the normal loop feed mode. During normal loop feed the SLIC is completely operational and performs all transmission and supervisory functions.
Where TA is maximum ambient temperature and JA is junction to air thermal resistance (and is package dependent). The entire term in parentheses yields the SLIC power dissipation. The power dissipation of the subscriber loop does not contribute to device junction temperature and is subtracted from the power dissipation term. Operating at 85oC, the maximum PLCC SLIC power dissipation is 1.18W. Likewise, the maximum SOIC SLIC power dissipation is 0.92W.
65
HC5517B
Circuit Operation and Design Information
SLIC DESIGN EQUATIONS FUNCTION 2-Wire to 4-Wire Gain EQUATION V OUT1 200 R ZO ------------------ = - ---------- ----------Z R V 2W 2w RF Z 2W V 2W ----------- = - 2 ---------------------------------- Z 2W + Z SLIC V RX DEFINITION OF TERMS VOUT1 = SLIC 4-wire Output V2w = Voltage across 2-wire load Z2W = 2-Wire Impedance V2W = Voltage Across 2-Wire Load VRX = SLIC 4-Wire Input Z2W = 2-Wire Impedance ZSLIC = SLIC Synthesized Impedance VOUT1 = SLIC 4-Wire Output VRX = SLIC 4-Wire Input Z2W = 2-Wire Impedance ZSLIC = SLIC Synthesized Impedance ILIMIT = Programmed Loop Current Limit RIL1 = Programming Resistor RIL2 = Programming Resistor Z2W = 2-Wire Impedance K = 100
4-Wire To 2-wire Gain
4-Wire To 4-wire Gain
Z 2W V OUT1 200 R ZO ------------------ = - 2 ---------------------------------- ----------- ----------Z 2W + Z SLIC Z 2W R RF V RX
Loop Current Limit Programming
( 0.6 ) ( R IL1 + R IL2 ) I LIMIT = ------------------------------------------------( 200xR IL2 ) R ZO = K ( Z 2W - 100 ) R RF = K 200 2
Impedance Matching
Through SLIC Ringing
The HC5517B uses linear amplification to produce the ringing signal. As a result the ringing SLIC can produce sinusoid, trapezoid or square wave ringing signals. Regardless of the wave shape, the ringing signal is balanced. The balanced waveform is another way of saying that the tip and ring DC potentials are the same during ringing.
Crest Factor Programming As previously mentioned, a single resistor is required to set the crest factor of the trapezoidal waveform. The only design variable in determining the crest factor is the battery voltage. The battery voltage limits the peak signal swing and therefore directly determines the crest factor. A set of tables will be provided to allow selection of the crest factor setting resistor. The tables will include crest factors below the Bellcore minimum of 1.2 since many ringing SLIC applications are not constrained by Bellcore requirements.
TABLE 1. CREST FACTOR PROGRAMMING RESISTOR FOR VBAT = -80V RTRAP 0 389 640 CF 1.10 1.15 1.20 RMS 65.0 62.6 60.0 RTRAP 825 964 1095 CF 1.25 1.30 1.35 RMS 57.6 55.4 53.3
Trapezoidal Ringing
The trapezoidal ringing waveform provides a larger RMS voltage to the handset. Larger RMS voltages to the handset provide more power for ringing and also increase the loop length supported by the ringing SLIC. One set of component values will satisfy the entire ringing loop range of the SLIC. A single resistor sets the open circuit RMS ringing voltage, which will set the crest factor of the ringing waveform. The crest factor of the HC5517B ringing waveform is independent of the ringing load (REN) and the loop length. Another robust feature of the HC5517B ringing SLIC is the ring trip detector circuit. The suggested values for the ring trip detector circuit cover quite a large range of applications. The assumptions used to design the trapezoidal ringing application circuit are listed below: * Loop current limit set to 25mA. * Impedance matching is set to 600 resistive. * 2-wire surge protection is not required. * System able to monitor RTD and SHD. Logic ringing signal is used to drive RC trapezoid network.
The RMS voltage listed in the table is the open circuit RMS voltage generated by the SLIC.
TABLE 2. CREST FACTOR PROGRAMMING RESISTOR FOR VBAT = -75V RTRAP 0 500 791 CF 1.10 1.15 1.20 RMS 60.9 58.3 55.9 RTRAP 1010 1190 1334 CF 1.25 1.30 1.35 RMS 53.7 51.6 49.7
66
HC5517B
TABLE 3. CREST FACTOR PROGRAMMING RESISTOR FOR VBAT = -65V RTRAP 0 660 1040 CF 1.10 1.15 1.20 RMS 52.5 49.8 47.8 RTRAP 1330 1600 1800 CF 1.25 1.30 1.35 RMS 45.9 44.1 42.5
HC5517B ADDITIONAL PULL UP RESISTOR
NU 23 RDI 20 RDO 21 VRING 24 DTRAP
VCC
RTRAP VRING CTRAP
TABLE 4. CREST FACTOR PROGRAMMING RESISTOR FOR VBAT = -60V RTRAP 0 740 1129 CF 1.10 1.15 1.20 RMS 48.2 45.6 43.7 RTRAP 1460 1760 2030 CF 1.25 1.30 1.35 RMS 42.0 40.4 38.8
FIGURE 1. APPLICATION CIRCUIT WIRING FOR SINGLE LOOP DETECTOR INTERFACE
(DUAL DETECTOR INTERFACE) MODE ACTIVE (LOGIC HI) F1 F0 VRING VALID DET SHD RTD SHD (LOGIC HI) RINGING ACTIVE
The voltages listed in the tables are driven from a logic source that will not drive the ringing input negative. If the ringing input is driven negative by 200mV, the peak-to-peak ringing amplitudes can be increased. Ringing Voltage Limiting Factors As the load impedance decreases (increasing REN), the source impedance of the SLIC during ringing slightly attenuates the ringing signal. If additional surge protection resistance must be used with the trapezoidal circuit, the loop length performance of the circuit will decrease proportionally to the added resistance in the Tip and Ring leads. For example if 30 protection resistors is used in each of the Tip and Ring leads, the ringing loop length will decrease by a total of 60. Low Level Ringing Interface The trapezoidal application circuit only requires a cadenced logic signal applied to the wave shaping RC network to achieve ringing. When not ringing, the logic signal should be held low. When the logic signal is low, Tip will be near ground and Ring will be near battery. When the logic signal is high, Tip will be near battery and Ring will be near ground. Loop Detector Interface The RTD output should be monitored for off hook detection during the ringing period. At all other times, the SHD should be monitored for off hook detection. The application circuit can be modified to redirect the ring trip information through the SHD interface. The change can be made by rewiring the application circuit, adding a pullup resistor to pin 23 and setting F0 low for the entire duration of the ringing period. The modifications to the application circuit for the single detector interface are shown in Figure 1. SLIC Operating State During Ringing The SLIC control pin F1 should always be a logic high during ringing. The control pin F0 will either be a constant logic high (two detector interface) or a logic low (single detector interface). Figure 2 shows the control interface for the dual detector interface and the single detector interface.
(SINGLE DETECTOR INTERFACE) MODE ACTIVE (LOGIC HI) F1 F0 VRING VALID DET SHD SHD SHD (LOGIC HI) RINGING ACTIVE
FIGURE 2. DETECTOR LOGIC INTERFACES
Additional Application Information
Transhybrid Balance Since the receive signal and its echo are 180 degrees out of phase, the summing node of an operational amplifier can be used to cancel the echo. Nearly all CODECs have an internal amplifier for echo cancellation. The circuit in Figure 3 shows the cancellation amplifier circuit.
RA VRX RB VOUT1 + RF
-
VO
FIGURE 3. TRANSHYBRID AMPLIFIER CIRCUIT
67
HC5517B
When the SLIC is matched to a 600 load and only the sense resistors are used, the 4-wire to 4-wire gain is equal to 5/12 as predicted by the design equations. Therefore, by configuring the transhybrid amplifier with a gain of 2.4 in the echo path, cancellation can be achieved. The following equations:
R F R F V O = - V RX ------- + V OUT1 ------- R A R B (EQ. 2)
The CODEC signal names may vary from different manufacturers, but the function provided will be the same. The DC reference from the CODEC is used to bias the analog signals between +5V and ground. The capacitors are required so that the DC gain is unity for proper biasing from the CODEC reference. Also, the capacitors block DC signals that may interfere with SLIC or CODEC operation.
Layout Guidelines and Considerations
The printed circuit board trace length to all high impedance nodes should be kept as short as possible. Minimizing length will reduce the risk of noise or other unwanted signal pickup. The short lead length also applies to all high gain inputs. The set of circuit nodes that can be categorized as such are: * * * * VRX pin 27, the 4-wire voice input (low gain input). -IN1 pin 13, the inverting input of the internal amplifier. VREF pin 3, the noninverting input to ring feed amplifier. VRING pin 24, the 20V/V input for the ringing signal.
Substituting the fact that VOUT1 is -5/12 of VRX
R F 5 R F V O = - V RX ------- - V RX - ----- ------- 12 R R A B
(EQ. 3)
Since cancellation implies that under these conditions, the output VO should be zero, set Equation 2 equal to zero and solve for RB .
RA R B = ------2.4 (EQ. 4)
Another outcome of the transhybrid gain selection is the 2-wire to 4-wire gain of the SLIC as seen by the CODEC. The 5/12 voltage gain in the transmit path is relevant to the receive input as well as any signals from the 2-wire side. Therefore by setting the VOUT1 gain to 2.4 in the previous analysis, the 2-wire to 4-wire gain was set to unity. Single Supply CODEC Interface The majority of CODECs that interface to the ringing SLIC operate from a single +5V supply and ground. Figure 4 shows the circuitry required to properly interface the ringing SLIC to the single supply CODEC.
For multi layer boards, the traces connected to tip should not cross the traces connected to ring. Since they will be carrying high voltages, and could be subject to lightning or surge depending on the application, using a larger than minimum trace width is advised. The 4-wire transmit and receive signal paths should not cross. The receive path is any trace associated with the VRX input and the transmit path is any trace associated with VTX output. The physical distance between the two signal paths should be maximized to reduce crosstalk, or separated by a ground trace. The operating mode control signals and detector outputs should be routed away from the analog circuitry. Though the digital signals are nearly static, care should be taken to minimize coupling of the sharp digital edges to the analog signals. The part has two ground pins, one is labeled AGND and the other BGND. Both pins should be connected together as close as possible to the SLIC. If a ground plane is available, then both AGND and BGND should be connected directly to the ground plane. A ground plane that provides a low impedance return path for the supply currents should be used. A ground plane provides isolation between analog and digital signals. If the layout density does not accommodate a ground plane, a single point grounding scheme should be used.
CODEC VRX RX OUT RA RF RB
-
+ TX IN
VOUT1 HC5517B +2.5V +
-
FIGURE 4. SINGLE SUPPLY CODEC INTERFACE
68
HC5517B Pin Descriptions
PLCC 1 2 3 4 SYMBOL AGND VCC VREF F1 DESCRIPTION Analog Ground - Serves as a reference for the transmit output and receive input terminals. Positive Voltage Source - normally +5V DC. An external voltage connected to this pin will override the internal VBAT/2 reference. Power Denial - An active low TTL compatible logic control input. When enabled, the output of the ring amplifier will ramp close to the output voltage of the tip amplifier. TTL compatible logic control input that controls multiplexing of the detector outputs. TTL compatible logic control input that must be tied high for proper SLIC operation. Switch Hook Detection - An active low TTL compatible logic output. Indicates an off-hook condition. Ring Trip Detection - An active low TTL compatible logic output. Indicates an off-hook condition when the phone is ringing. May be used to indicate ring trip or ground key detection. A TTL logic input. A low on this pin will keep the SLIC in a power down mode. The TST pin, in conjunction with the ALM pin, can provide thermal shutdown protection for the SLIC. Thermal shutdown is implemented by a system controller that monitors the ALM pin. When the ALM pin is active (low), the system controller issues a command to the TST pin (low) to power down the SLIC. The timing of the thermal recovery is controlled by the system controller. A TTL compatible active low output which responds to the thermal detector circuit when a safe operating die temperature has been exceeded. Loop Current Limit - used with VTX to set the short loop current limiting conditions. The 4-wire output of the SLIC. The inverting input of the impedance matching amplifier. The non-inverting input is internally connected to AGND. An analog input connected to the TIP (more positive) side of the subscriber loop through a feed resistor. Functions with the RING terminal to receive voice signals and for loop monitoring purpose. An analog input connected to the RING (more negative) side of the subscriber loop through a feed resistor. Functions with the TIP terminal to receive voice signals and for loop monitoring purposes. This is an internal sense mode that must be tied to RING SENSE 1 for proper SLIC operation. Also used during unbalanced ringing. Receive Input, 4-Wire Side - A high impedance analog input. AC signals appearing at this input drive the Tip Feed and Ring Feed amplifiers differentially. Not used in this application. This pin should be left floating. A low impedance analog voltage output which is proportional to the subscriber loop current. Since the DC level of this output varies with loop current, capacitive coupling to IN1- is necessary. TTL compatible input to drive the ring relay driver during unbalanced ringing. Open collector relay driver used during unbalanced ringing. Battery Ground - All loop current and some quiescent current flows from this terminal. Not used in this application. This pin should be either grounded or left floating. Low level ringing signal input. Output of the tip line feed amplifier. Output of the ring line feed amplifier. The negative battery source, all loop current flows into this terminal. Ring Trip Input - This pin is connected to the external negative peak detector output for ring trip detection.
5 6 7 8
F0 RS SHD RTD
9
TST
10
ALM
11 12 13 14
ILIMIT OUT1 -IN1 TIP SENSE
15
RING SENSE 1
16
RING SENSE 2
17
VRX NU VTX RDI RDO BGND NU VRING TF RF VBAT RTI
18 19
20 21 22 23 24 25 26 27 28
69
HC5517B Pinouts
HC5517B (PLCC) TOP VIEW
AGND VREF VBAT VCC RTI RF F1 AGND 1 VCC 2 25 TF 24 VRING 23 NU 22 BGND 21 RDO 20 RDI 19 12 OUT 1 13 -IN 1 14 TIP SENSE 15 RING SENSE 1 16 RING SENSE 2 17 VRX 18 NU VTX VREF 3 F1 4 F0 5 RS 6 SHD 7 RTD 8 TST 9 ALM 10 ILIMIT 11 ILIMIT 11 OUT 1 12 -IN 1 13 TIP SENSE 14
HC5517B (SOIC) TOP VIEW
28 RTI 27 VBAT 26 RF 25 TF 24 VRING 23 NU 22 BGND 21 RDO 20 RDI 19 VTX 18 NU 17 VRX 16 RING SENSE 2 15 RING SENSE 1
4 F0 RS SHD RTD TST ALM 5 6 7 8 9 10
3
2
1
28
27
26
Trapezoidal Ringing Application Circuit
U1 HC5517B TIP 14 RS1 25 TIP SENSE TF ILIMIT RF RING SENSE 2 RING SENSE 1 -IN1 OUT1 VCC AGND RTI 28 RRT3 13 12 VTX 19 11 VRX 17 RIL2 RIL1 CAC 15 RRF RZO V-XMIT RRT2 RRT1 CRT DRT CRX V-REC
26 16 RS2 RING
VCC CPS1 CPS2 VBAT
2 15
22 BGND 27
VBAT VRING
24 CIL DTRAP
RTRAP VRING CTRAP
F1 F0 VCC TST
4 5 6 9 20
VREF F1 F0 RS TST RDI SHD RTD ALM
3
7 8 10
SHD RTD ALM
FIGURE 5. TRAPEZOIDAL RINGING APPLICATION CIRCUIT
70
HC5517B HC5517B Trapezoidal Ringing Application Circuit Parts List
COMPONENT U1 - Ringing SLIC RS1, RS2 RZO , RIL1 RRT1 RRT2 RRT3 RRF VALUE HC5517B 49.9 56.2k 49.9k 1.5M 51.1k 45.3k TOLERANCE N/A 1% 1% 1% 1% 1% 1% RATING N/A
1/ W 2 1/ W 8 1/ W 8 1/ W 8 1/ W 8 1/ W 8
COMPONENT RIL2 RTRAP CPS1 , CPS2 CIL , CRT , CAC , CRX CTRAP DRT , DTRAP
VALUE 7.68k User-Defined 0.1F 0.47F 4.7F 1N914
TOLERANCE 1% 1% 10% 10% 10%
RATING
1/ W 8 1/ W 8
100V 50V 10V
Generic Rectifier Diode
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
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Price & Availability of HC5517B

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